Designers analyze the timing of circuit designs in order to verify that a circuit implemented from the circuit design will operate as intended. Setup and hold time violations may be identified and paths of the circuit design adjusted accordingly. A critical path is generally recognized as any path that has a setup or hold time violation.
Static timing analysis (STA) uses timing models of circuit elements to determine delays of paths in the circuit design. The timing models associate delay values with circuit elements, and the delay of a path can be computed as the sum of the delay values of the circuit elements on the path. STA sometimes produces results that are too optimistic or overly pessimistic. If the STA results are too optimistic, a circuit path may violate timing constraints even though STA indicated the path is legal. If the STA results are too pessimistic, a circuit path may have enough slack to have supported a faster clock speed without violating timing constraints.
Statistical static timing analysis (SSTA) uses statistical models of circuit elements to improve the quality of timing analysis. Instead of using different delay values that are associated with different corners of a circuit element, the circuit element has associated statistical characterizations of delays.
Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Approaches used in SSTA of ASIC circuit designs are impractical for application to circuit designs targeted to programmable ICs having FPGAs. FPGA timing models are abstracted timing models that may involve two transistors to hundreds of transistors and several stages of logic/custom circuits. In contrast, ASIC timing models describe individual cells in standard cell libraries. In addition, metal interconnect delay calculation for ASIC circuit designs is performed on-the-fly using several model order reduction techniques. However, in FPGAs, interconnect models are discrete, pre-calculated models and may contain many active elements.